Computer systems requiring large amounts of memory capacity are often designed to allow the purchaser or user of the computer system to select the amount of memory in the system. The purchaser of the computer system can equip the system with the amount of memory necessary for his current needs but have the ability to expand at a later date if his need for memory capacity increases.
A system with expandable memory, typically provides a memory subsystem comprising a memory backplane in which memory cards can be installed as needed. Typically, the memory backplane comprises a series of slots in which memory cards can be inserted. The slots are interfaced to a memory controller which supervises the memory operations and memory read or write requests from the central processing unit (CPU). The memory cards (or memory boards) contain a group of memory chips thereon which interface to logic devices contained on the same memory board. When the cards are inserted into the slots on the memory backplane, the logic devices become electrically connected to address and data buses interfaced to the memory controller of the computer system. The amount of memory on each card is not necessarily fixed and can be one of several values thus affording the purchaser even greater flexibility in terms of selectable memory capacity.
In a system as just described wherein the total available memory as well as memory available on each card are not fixed, means must be provided for communicating to the computer operating system the size and location of the available memory. In order to know how much physical memory is in the system, the operating system must "know" which slots are occupied by memory cards, the amount of memory available on each card, and the addresses of the memory on each card.
The memory available on any given card is a consecutive block of addresses and therefore the memory controller and operating system need only know the starting address and ending address of the memory space available on that card. Once this information is available to the operating system, it can select the memory card containing the memory address required for any memory operation.
In systems having very large amounts of memory, the system can be designed such that a single address addresses a large block of data, for instance, eight double words. After the data is retrieved from an address location, the system can break up the data into smaller components to extract the data as required.
Further, memory systems traditionally have comprised more than one memory subsystem, each of which comprises a memory controller and a series of memory boards plugged into the slots of a memory backplane.
One method used in the prior art for selecting the appropriate card for a memory operation is to have a unique combination of "ID" bits for each memory slot hardwired in the memory backplane. When a memory location (or address) is sent out on the address bus for a requested memory operation, the ID bits for each memory board are compared with certain bits in the requested address. If the bits match, as they should for one and only one board, that board is selected for the memory operation.
This method will be more particularly described with respect to a memory subsystem having addresses of A bits in length, 2.sup.C memory slots, and a maximum memory board density of 2.sup.B bytes. The low order A-B bits of the address are used as the address on the selected board. The remaining high order bits, which should comprise C bits, comprise the address bits which are compared against the hardwired ID bits to select the appropriate board. The ID bits for each slot, of course, also comprise C bits. This board selection scheme is easy to implement if only one size memory board is available in the system. However, where the memory board density may be one of several values a problem exists because any board smaller than the maximum density board cannot support the full address space supplied by each slot. Since the low order A-B bits of each address constitutes a number of memory addresses which exceeds the actual amount of memory in any board smaller than the maximum density board, large gaps of memory exist in the range of addresses. Typically, what is done to prevent the addressing of an empty space is that one or more of the highest of the low order A-B bits are reserved for use as additional select bits. For instance, in a system where there are two possible memory board sizes of X and 2X, the highest of the low order bits is used as an additional select bit. If this bit is zero, then the board can be selected; if the bit is one, however, then the board is not selected since the upper half of the memory reserved for this slot is vacant. If, for example, the possible memory board sizes were X and 4X, then the two highest of the low order A-B address bits are used as additional select bits. In this situation, if these bits are 00, the board is selected; if the bits are anything but 00, then the board is not selected.
Some means must be provided in the system for mapping out the holes from the available address space. Typically, when the operating system tests and initializes the memory subsystem at power up, it locates the memory holes by attempting to write and read each memory location. The operating system detects the memory locations that are vacant by receiving missing memory module reports from the memory hardware and reports this as a missing memory module. The operating system records the missing memory module locations as nonexistent locations in address space.
This scheme has many substantial shortcomings. First, additional software is required to find the holes in memory. Secondly, with the continuing increases in memory board sizes in the art, finding the holes can be a very time consuming task, adding to the time to power up the system. Further, there are usually certain memory locations at the beginning of the memory which are reserved for use of the memory controller. Therefore, a memory board must be placed in the first slot. Should the system installer neglect to place a memory board in the first slot, then the system would not operate.
In a system having two (or more) memory subsystems, memory contained in the first subsystem may be combined with the memory contained in the second subsystem by either high order interleaving or low order interleaving. In high order interleaving, the first memory subsystem provides addresses zero through X. The second memory subsystem simply provides addresses X+1 through Z. In low order interleaving in a system having only two memory subsystems, for example, the first memory subsystem services the even addresses contained between the beginning address and ending address, zero to Z. The second memory subsystem services the odd addresses contained within the zero to Z address space. If low order interleaving is implemented in the above example of a system with two memory subsystems, the LSB (least significant bit) of the address is used for selecting the memory subsystem which is to service the memory operation. If the LSB is a 0, then subsystem 1 (servicing the even addresses) would respond to the address request. If the LSB is a 1, then memory subsystem 2 would respond to the address request. In the prior art, in order to implement low order interleaving, it was necessary that the holes in each of the memory subsystems parallel the holes in all other memory subsystems. Therefore, in the prior art, the corresponding slots of the memory backplane of each subsystem must contain the same size memory card.
It is an object of the present invention to provide an improved method and apparatus for selecting the memory board containing the memory locations for servicing a memory operation of a computer system.
It is another object of the present invention to eliminate holes in the memory space of a computer system which provides flexible memory capacity.
It is yet a further object of the present invention to provide a computer system requiring less restrictions on the size and placement of memory boards which may be inserted in a memory backplane.
It is a further object of the present invention to provide a combined hardware and software method and apparatus for determining the size of memory boards in a memory backplane of a computer system and selecting the appropriate memory board for servicing a memory operation.
It is an additional object of the present invention to provide an improved memory board selection scheme for a computer system.
It is yet another object of the invention to provide a combined hardware and software method an apparatus for determining the size of memory boards in a memory backplane and which allows the memory subsystem to operate regardless of the number, density, and placement of memory boards in the memory backplane.
It is one more object of the present invention to provide a computer system having multiple memory subsystems whose memory can be arranged alternatively by high order interleaving or low order interleaving.
It is another object of the present invention to provide a computer system having multiple memory subsystems which are low order interleaved in which the memory cards inserted in corresponding slots of each subsystem backplane need not be of equal capacity.